This disclosure relates in general to IC signal interfaces and in particular to IC signal interfaces related to JTAG based test, emulation, debug, and trace operations. This disclosure is a further development of a previous disclosure (Ser. No. 12/887,672) titled “Optimized JTAG Interface”. The previous material of Ser. No. 12/887,672 is completely incorporated into this new disclosure. The new material of this disclosure starts with FIG. 29.